The present invention relates to a chip-like electronic component suitable for use in the manufacture of a semiconductor device and a method of manufacturing the same, and in particular, it relates to a pseudo wafer for use in the manufacture of the same and a method therefor.
Recently, demands for a more compact, thinner and lightweight design of a portable electronic device which is typically represented by a digital video camera, a digital portable telephone, a note-size personal computer and the like are growing, thereby it is becoming a most important key point how to improve a surface packaging density on their semiconductor parts. For this purpose, a development of a more compact CSP (Chip Scale Package) in place of package ICs (QFP (Quad flat package) or the like) and a proliferation of a bare chip packaging based on the flip chip method which is now partially adopted and may lead to an ultimate semiconductor high density packaging technology are strongly desired.
By way of example, as a typical bump forming technique in the above-mentioned flip chip packaging method, there are a method for forming Au bumps on an Al electrode pad by using the Au-stud bump method or the electroplating method, and a method for forming solder bumps in batch by using the electroplating method or the vapor deposition method. However, in a commercial application where a low cost flip chip packaging is preferred, it is advantageous not to form bumps after the chip is prepared as in the Au stud bump method, but to form bumps in batch in its preceding stage of wafer.
This wafer batch processing method described above clearly indicates a trend of technology in the future in consideration of a recent advancement of large scaled wafers (from 150 mmφ to 200 mmφ and to 300 mmφ), and an increasing number of chip connection pins in LSIs (large scaled integrated-circuits).
Conventional bump forming methods will be described in the following.
FIG. 9 is an example showing an Au stud bump 24. On a surface of an Al pad 55 formed on a semiconductor chip 25 which is diced from a wafer there is formed the Au stud bump 24 using a wire bonding method. FIG. 10 shows an example in which a silicon substrate (wafer) 51 having, for example, an input/output circuit 22 and a device region (memory) 23 formed thereon, is processed in batch so as to form solder bumps 62 in its wafer level. By way of example, reference numeral 21 depicts a scribe line.
Further, FIGS. 11A-11E show steps of forming bumps on a wafer in batch in combination of Ni electroless plating and solder paste printing methods in order to reduce the cost of manufacture. FIG. 11A depicts a silicon substrate (wafer) having an SiO2 film formed thereon, and FIG. 11B depicts an enlarged part of a chip portion including its electrodes. In FIGS. 11A and 11B, numeral 51 depicts an Si substrate (wafer), 55 depicts an Al electrode pad, and others depict a SiO2 film and a passivation film comprising Si3N4 film, SiO2 film or a polyimide film.
In FIG. 11C, exclusively on a perforated upper surface of the Al electrode pad 55, an Ni electroless plating layer (UBM: under bump metal) is formed selectively by the Ni electroless plating method. This Ni electroless plating layer serving as a UBM for supporting electric connection between the Al electrode pad 55 and the solder bump can be formed easily by the steps of pretreating the Al electrode pad 55 with a phosphoric acid etching solution, substitution-precipitating Zn by a Zn processing, and dip-coating in a Ni—P plating vessel.
FIG. 11D shows a state in which a solder paste 59 is transferred onto the Ni electroless plating layer (UBM) through a metal screen mask 52 by a printing method. FIG. 11E shows a state in which the solder paste 59 is fused by a wet back method (hot fusing) to form a solder bump 62. Thereby, without use of a photo processing, the solder bump 62 can be formed easily by using the Ni electroless plating method and the solder paste screen printing method, or the like.
On the other hand, the CSP which is an approach to a high density packaging of LSIs by minimizing respective chips thereof is comprised of several common circuit blocks as viewed from the standpoint of a digital device circuit block diagram, and there is emerging such a process to provide these common circuit blocks in a multi package or in a MCM (multi chip module). Provision of SRAM (static RAM), flash memory and a microcomputer in one chip package in a digital portable telephone is one example thereof.
This MCM technology is expected to show a significant advantage also in a one-chip system LSI of a recent development. Namely, when integrating memory, logic and analog LSIs on one chip, different LSI fabrication processes must be handled in a same wafer processing step, thereby substantially increasing the number of masks and processing steps, and its TAT (turnaround time) for development being prolonged. Also, a low yield in production resulting from the increased steps of processing is a serious problem which cannot be ignored.
For this reason, it is considered to be promising that respective LSIs are fabricated discretely, then they are packaged in an MCM. An example of such MCM packaging is shown in FIGS. 12A and 12B.
FIGS. 12A and 12B show a wire-bonding method whereby each chip 62 mounted on a circuit substrate 60 is electrically connected using a wire 61 therebetween. Further, FIGS. 13A-13C show a flip chip method whereby each chip 64 is connected to an electrode 63 on a circuit substrate 60 in a state of facedown. For the purpose of a more compact and thinner design of the device, the flip chip method indicated in FIGS. 13A-13C is considered to be advantageous. Further, for minimization of connecting wire length necessary for a faster speed in the future, and in consideration of impedance variations in respective connections, the flip chip method is considered to take over.
For the MCM using the flip chip method, there are proposed various connecting methods including such one that forms Au-stud bumps on a surface of an Al electrode pad 55 provided on each LSI of a plurality of different types of LSIs, and electrically connects with its circuit substrate via an anisotropic conductive film (ACF), another method by a press bonding using a resin paste, and other ones that use plated Au bumps, Ni electroless plated bumps, soldered bumps or the like as its bumps. FIG. 13C shows an example which ensures a lower electric resistance connection to the substrate 60 by means of an intercalation bonding via a solder bump 65.
The above-mentioned respective bump-forming methods have been completed already and started to be used for mass production. For example, the Au stud bump 24 indicated in FIG. 9 is formed by a method of forming a bump per chip. This method of forming a bump per chip is widely used as a simple bump forming method using existing facilities, however, there is a problem that as the number of termination pins increases, the cost of forming bumps will increase accordingly.
Further, in a recent trend of a lower voltage driving of LSIs, because of a problem of a voltage drop in an Al wiring layer, a provision of an area pad not limiting to a peripheral electrode pad but including additional electrode pads also on active elements is required. However, the Au stud bump 24 in FIG. 9 is not suitable for use as this area pad in consideration of a bonding load and a susceptibility to damage. Still further, there is such a problem that a packaging of Au stud bump chips is done by press bonding of a piece by piece basis, and has a difficulty of mounting on both surfaces.
On the other hand, the wafer batch solder bump forming method is advantageous in terms of packaging because it can be applied to the provision of the area pad, and enables a batch reflow or a double side mounting. However, it has a disadvantage when applying to the processing of a leading-edge wafer which normally has a low yield of production because a cost of production per non-defective chip will substantially increase.
Namely, with reference to FIG. 14, which indicates a semiconductor wafer 53 fabricated by a conventional wafer batch processing, nevertheless a high yield of production is required for the leading-edge LSIs, the number of defective chips 20 partitioned by a scribe line 21 and marked with “x” is actually greater than the number of non-defective chips 3 marked with “o”.
Further, there has been such a problem that if bare chips are purchased from external manufacturers or venders, it is extremely difficult to form bumps on them due to a varied design specification. Namely, although the above-mentioned two types of bump forming methods have their own merits, they cannot be used in all fields, but are actually used individually taking the most use of their own merits. The wafer batch bump forming method which has a high yield is advantageous for use in such a case where the number of terminals accommodated within a single wafer is large (for example, 50000 terminals/wafer), or for forming low damage bumps applicable to the area pad. Further, the Au stud bump is advantageous for use in a bump treatment per chip in a case where the bare chips are purchased by lot, or for a simple bump treatment.
Still further, when the semiconductor wafer 53 indicated in FIG. 14 is diced along the scribe line 21, a damage such as a stress or a crack occurs in the chip due to its dicing, which may lead to a failure. Furthermore, if a process of forming solder bumps in batch on the semiconductor wafer 53 which includes both the non-defective chips 3 and the defective chips 20 is allowed to proceed, the process applied to the defective chips 20 is wasted, thereby increasing the cost of manufacture.
In Japanese Patent Application Publication Laid-Open Hei 9-260581, a method of forming a wiring layer for interconnection between devices is disclosed whereby a plurality of semiconductor chips are firmly bonded on a silicon wafer, embedded into a resin formed on a substrate made of alumina or the like under pressure, then peeled off so as to provide a flat wafer surface and form the wiring layer for interconnection between the devices on this flat wafer surface by photolithography.
According to this conventional method, it is proposed that a wafer batch processing becomes possible and a low cost manufacture thereof by a merit of mass production is attained. However, because there exists a hard substrate made of alumina described above under the bottom surface of each semiconductor chip arrayed on the wafer, at the time of scribing and cutting into a dice, the hard substrate present under the bottom surface of the chip must be cut together with the resin between adjacent chips, thereby likely to damage a cutter blade. In addition, although the sidewalls of the chip are covered with the resin, there exists only the hard substrate different from the resin on the bottom surface thereof, therefore, there is such a problem that the bottom surface of the chip is not protected effectively and adhesion therebetween is weak.